1. Field of the Invention
The present invention relates to digital signal level translators, and in particular, to digital signal level translators for converting unbalanced digital signals to balanced digital signals with virtually no static power consumption.
2. Description of the Related Art
Digital signal level translators have become increasingly important in digital signal systems as the types and operating conditions of the various digital logic families have increased (e.g. TTL, ECL, CMOS, BIMOS). Their importance has become even greater as more and more systems are designed to more readily interface with one another in a manner which is transparent to the user.
One common type of digital signal level translator is designed for translating transistor-transistor logic ("TTL") signals to balanced digital signals, such as those used in complementary metal oxide semiconductor field effect transistor ("MOSFET") logic circuits. Such translators are required to convert the unbalanced TTL signals, bounded by zero and +5 volts dc, to balanced digital signals, typically bounded by equal positive and negative voltages (e.g. .+-.10 volts dc). Various embodiments of such translators currently exist, but suffer from a number of problems, such as wasteful static power dissipation and poor load-driving capability, or "fan out."
Referring to FIG. 1, a conventional digital signal level translator consists of a differential amplifier 10, a gate-driven complementary MOSFET latch 12, an inverter 14 and a biasing circuit 16 (discussed further below), connected as shown. The input signal 18, an unbalanced TTL signal bounded by circuit ground and VCC (e.g. +5 volts dc), is initially converted by the differential amplifier 10 to an unbalanced differential signal 20 bounded by circuit ground and VDD (e.g. +10 volts dc). This unbalanced differential signal 20 is then converted by the latch 12 to a balanced output signal 22, bounded by VDD and VSS (e.g. -10 volts dc).
This type of translator suffers from a number of problems. First, the differential amplifier 10, operating as an analog comparator circuit and driven with a current source 24 and biased at a threshold voltage supplied by the biasing circuit 16, is always conductive, i.e. dc biasing current is always flowing through one of its branches. Further, dc biasing current constantly flows through the threshold biasing circuit 16. Thus, static power consumption is relatively high.
Second, the output latch 12, being a cross-coupled circuit, has poor fan out capacity and is relatively slow. The slow switching speed of the latch 12 can be compensated somewhat by increasing the current through the differential amplifier 10 by varying the bias voltage VBIAS on its current source 24. However, this further aggravates the aforementioned problem of high static power consumption.
Referring to FIG. 2A, the inverter 14 consists of a P-type MOSFET 26 and an N-type MOSFET 28 whose gates are connected together and whose drains are connected together. The source of the P-type MOSFET 26 is connected to VCC and the source of the N-type MOSFET 28 is connected to circuit ground. This type of complementary MOSFET inverter and its operation are well known in the art.
Referring to FIG. 2B, the biasing circuit 16 consists of a P-type MOSFET 30 and an N-type MOSFET 32. However, in this circuit, the gates and drains of both transistors 30, 32 are all connected together. This results in both transistors 30, 32 being biased on, and thereby effectively operating as a voltage divider between VCC and ground. As is known in the art, the actual DC voltage potential available at the output can be preselected by appropriately scaling the device geometries (e.g. the channel widths and lengths) of the two MOSFETs 30, 32.
Referring to FIG. 3, another conventional digital signal level translator consists of a differential amplifier 34, a totem-pole output amplifier 36, an inverter 14 and biasing circuit 16, connected as shown. This circuit is an improvement over that of FIG. 1 in that the output amplifier 36 has improved fan out and speed as compared to the output latch 12 of FIG. 1. However, static power consumption is still a problem due to the constant current conduction of the differential amplifier 34, driven by a current source 38 and threshold biasing circuit 16, as discussed above.
Referring to FIG. 4, another conventional digital signal level translator consists of an input latch 40, an output latch 42 and two inverters 14, connected as shown. The gate-driven input latch 40 converts the unbalanced TTL input signal 18 to a differential unbalanced signal 44, which in turn, is converted to a balanced output signal 22. This translator circuit consumes virtually no static power, since neither of its stages 40, 42 conducts current when latched in either of their two logic states. However, this translator circuit still suffers from poor fan out and switching speed, particularly since both stages 40, 42 are serially connected cross-coupled circuits.
Referring to FIG. 5, another conventional digital signal level translator consists of an input latch 44, an output latch 46 and two inverters 14, connected as shown. This translator circuit is substantially equivalent to that of FIG. 4, with the exception that the input latch 44 is source-driven rather than gate-driven. Hence, although this translator circuit also consumes virtually no static power, it too suffers from poor fan out and speed.